/* verilator lint_off UNUSEDSIGNAL */
/* verilator lint_off UNDRIVEN */
`include "defines.svh"
`include "axi_defines.svh"

module axi_clint(
    input  logic reset,
    input  logic clk,

    // AXImaster <-> AXIslave
    input  logic arvalid,
    input  addr_t araddr,
    output logic arready,

    input  logic rready,
    output data_t rdata,
    output resp_t rresp,
    output logic rvalid
);
    logic ar_shake;
    assign ar_shake = arready & arvalid;

    // R
    always_comb begin
        if(reset) begin
            arready = `OFF;
        end else begin
            arready = `ON;
        end
    end
    always_ff @(posedge clk) begin
        if (reset) begin
            rvalid <= `OFF;
        end else if(ar_shake) begin
            rvalid <= `ON;
        end else begin
            rvalid <= `OFF;
        end
    end
    
    // ADDR
    logic is_low;
    assign is_low = araddr[3:0] == 4'h8;

    // DATA
    reg [63:0] mtime;
    always_ff @(posedge clk) begin
        if(reset) begin
            mtime <= `NULL;
        end else begin
            mtime <= mtime + 1'b1;
        end

        if(reset) begin
            rdata <= `NULL;
        end else if(ar_shake) begin // 有读请求时
            rdata <= is_low ? mtime[31:0] : mtime[63:32];
            rresp <= `OKAY;
        end else begin
            rdata <= `NULL;
            rresp <= `DECERR;
        end
    end


endmodule
